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| 0 R QPro Virtex 2.5V Radiation Hardened FPGAs 0 2 DS028 (v1.2) November 5, 2001 Preliminary Product Specification * * Complete support for Unified Libraries, Relationally Placed Macros, and Design Manager Wide selection of PC and workstation platforms Unlimited reprogrammability Four programming modes Features * * * * * * * * 0.22 m 5-layer epitaxial process QML certified Radiation hardened FPGAs for space and satellite applications Guaranteed total ionizing dose to 100K Rad(si) Latch-up immune to LET = 125 MeV cm2/mg SEU immunity achievable with recommended redundancy implementation Guaranteed over the full military temperature range (-55C to +125C) Fast, high-density Field-Programmable Gate Arrays * * * Densities from 100k to 1M system gates System performance up to 200 MHz Hot-swappable for Compact PCI 16 high-performance interface standards Connects directly to ZBTRAM devices Four dedicated delay-locked loops (DLLs) for advanced clock control Four primary low-skew global clock distribution nets, plus 24 secondary global nets LUTs configurable as 16-bit RAM, 32-bit RAM, 16-bit dual-ported RAM, or 16-bit Shift Register Configurable synchronous dual-ported 4k-bit RAMs Fast interfaces to external high-performance RAMs Dedicated carry logic for high-speed arithmetic Dedicated multiplier support Cascade chain for wide-input functions Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset Internal 3-state bussing IEEE 1149.1 boundary-scan logic Die-temperature sensing device SRAM-based in-system configuration Available to Standard Microcircuit Drawings. Contact Defense Supply Center Columbus (DSCC) for more information at http://www.dscc.dla.mil 5962-99572 for XQVR300 5962-99573 for XQVR600 5962-99574 for XQVR1000 Description The QProTM VirtexTM FPGA family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 5-layer-metal 0.22 m CMOS process. These advances make QPro Virtex FPGAs powerful and flexible alternatives to mask-programmed gate arrays. The Virtex radiation hardened family comprises the three members shown in Table 1. Building on experience gained from previous generations of FPGAs, the Virtex family represents a revolutionary step forward in programmable logic design. Combining a wide variety of programmable system features, a rich hierarchy of fast, flexible interconnect resources, and advanced process technology, the QPro Virtex family delivers a high-speed and high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market. Refer to the "VirtexTM 2.5V Field Programmable Gate Arrays" commercial data sheet for more information on device architecture and timing specifications. Multi-standard SelectI/OTM interfaces Built-in clock-management circuitry Hierarchical memory system - * Flexible architecture that balances speed and density - * Supported by FPGA FoundationTM and Alliance Development Systems (c) 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS028 (v1.2) November 5, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 1 QPro Virtex 2.5V Radiation Hardened FPGAs Table 1: QPro Virtex Radiation Hardened Field-Programmable Gate Array Family Members. Device XQVR300 XQVR600 XQVR1000 System Gates 322,970 661,111 1,124,022 CLB Array 32x48 48x72 64x96 Logic Cells 6,912 15,552 27,648 Maximum Available I/O 316 316 404 Block RAM Bits 65,536 98,304 131,072 Max Select RAM Bits 98,304 221,184 393,216 R Radiation Specifications(1) Symbol TID Description Total Ionizing Dose Method 1019, Dose Rate ~9.0 rad(Si)/sec SEL Single Event Latch-up Immunity Heavy Ion Saturation Cross Section LET > 125 MeV cm2/mg SEUFH SEU CH SEUCP SEUBH Single Event Upset CLB Flip-flop Heavy Ion Saturation Cross Section Single Event Upset Configuration Latch Heavy Ion Saturation Cross Section Single Event Upset Configuration Latch Proton (63 MeV) Saturation Cross Section Single Event Upset BRAM Bit Heavy Ion Saturation Cross Section Notes: 1. For more information, refer to "Radiation Test Results of the Virtex FPGA for Space Based Reconfigurable Computing" and "SEU Mitigation Techniques for Virtex FPGAs in Space Applications" at http://www.xilinx.com/products/hirel_qml.htm. Min 100 Max - Units krad(Si) (cm2/Device) - 0 - 6.5E - 8 (cm2/Bit) (cm2/Bit) (cm2/Bit) (cm2/Bit) - 8.0E - 8 - 2.2E - 14 - 1.6E - 7 2 www.xilinx.com 1-800-255-7778 DS028 (v1.2) November 5, 2001 Preliminary Product Specification R QPro Virtex 2.5V Radiation Hardened FPGAs Virtex Electrical Characteristics Based on preliminary characterization. Further changes are not expected. All specifications are representative of worst-case supply voltage and junction temperature conditions. The parameters included are common to popular designs and typical applications. Contact the factory for design considerations requiring more detailed information. Virtex DC Characteristics Absolute Maximum Ratings Symbol VCCINT VCCO VREF VIN (3) Description Supply voltage relative to GND Supply voltage relative to GND Input reference voltage Input voltage relative to GND Voltage applied to 3-state output Longest supply voltage rise time from 1V to 2.375V Storage temperature (ambient) Junction temperature Using VREF Internal threshold Min/Max -0.5 to 3.0 -0.5 to 4.0 -0.5 to 3.6 -0.5 to 3.6 -0.5 to 5.5 -0.5 to 5.5 50 -65 to +150 +150 Units V V V V V V ms C C VTS VCC TSTG TJ Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 2. Power supplies may turn on in any order. 3. For protracted periods (e.g., longer than a day), VIN should not exceed VCCO by more that 3.6V. Recommended Operating Conditions Symbol VCCINT VCCO TIN TIC Description Supply voltage relative to GND Supply voltage relative to GND Input signal transition time Initialization temperature range(4) XQVR300 XQVR600 XQVR1000 TOC Operational temperature range(5) XQVR300 XQVR600 XQVR1000 ICCINTQ Quiescent VCCINT supply current XQVR300 XQVR600 XQVR1000 ICCCCOQ Quiescent VCCO supply current XQVR300 XQVR600 XQVR1000 Device Min 2.5 - 5% 1.2 -55 -55 -40 -55 -55 -55 Max 2.5 + 5% 3.6 250 +125 +125 +125 +125 +125 +125 150 200 200 4.0 4.0 4.0 Units V V ns C C C C C C mA mA mA mA mA mA Notes: 1. Correct operation is guaranteed with a minimum VCCINT of 2.25V (Nominal VCCINT - 10%). Below the minimum value stated above, all delay parameters increase by 3% for each 50 mV reduction in VCCINT below the specified range. 2. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C. 3. Input and output measurement threshold is ~50% of VCC. 4. Initialization occurs from the moment of VCC ramp-up to the rising transition of the INIT pin. 5. The device is operational after the INIT pin has transitioned high. DS028 (v1.2) November 5, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 3 QPro Virtex 2.5V Radiation Hardened FPGAs R QPro Virtex Pinouts Device/Package Combinations and Maximum I/O Maximum User I/O (excluding dedicated clock pins) Package CB228 CG560 XQVR300 162 XQVR600 162 XQVR1000 404 Pinout Tables See the Xilinx WebLINX web site (http://www.xilinx.com/partinfo/databook.htm) for updates or additional pinout information. For convenience, Table 2 and Table 3 list the locations of special-purpose and power-supply pins. Pins not listed are user I/Os. Table 2: Virtex Ceramic Column Grid (CG560) Pinout Pin Name GCK0 GCK1 GCK2 GCK3 M0 M1 M2 CCLK PROGRAM DONE INIT BUSY/DOUT D0/DIN D1 D2 D3 D4 D5 D6 D7 WRITE CS TDI Device XQVR1000 CG560 AL17 AJ17 D17 A17 AJ29 AK30 AN32 C4 AM1 AJ5 AH5 D4 E4 K3 L4 P3 W4 AB5 AC4 AJ4 D6 A2 D5 VCCO, Bank 2 VCCO, Bank 0 VCCO, Bank 1 VCCINT (VCCINT pins are listed incrementally. Connect all pins listed for both the required device and all smaller devices listed in the same package.) Table 2: Virtex Ceramic Column Grid (CG560) Pinout (Continued) Pin Name TDO TMS TCK DXN DXP Device XQVR1000 CG560 E6 B33 E29 AK29 AJ28 A21, B12, B14, B18, B28, C22, C24, E9, E12, F2, H30, J1, K32, M3, N1, N29, N33, U5, U30, Y2, Y31, AB2, AB32, AD2, AD32, AG3, AG31, AJ13, AK8, AK11, AK17, AK20, AL14, AL22, AL27, AN25 A22, A26, A30, B19, B32 A10, A16, B13, C3, E5 B2, D1, H1, M1, R2 4 www.xilinx.com 1-800-255-7778 DS028 (v1.2) November 5, 2001 Preliminary Product Specification R QPro Virtex 2.5V Radiation Hardened FPGAs Table 2: Virtex Ceramic Column Grid (CG560) Pinout (Continued) Pin Name VREF, Bank 6 Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 7 Within each bank, if input reference voltage is not required, all VREF pins are general I/O. GND Device XQVR1000 CG560 V29, Y32, AA30,AD31, AE29, AK32, AE31, AH30 D31, E31, G31, H32, K31, P31, T31, L33 A1, A7, A12, A14, A18, A20, A24, A29, A32, A33, B1, B6, B9, B15, B23, B27, B31, C2, E1, F32, A6, D7, D10, D11, D13, D16, E7, E15 B3, G5, H4, K5, L5, N5, P4, R1 V4, W5, AA4, AD3, AE5, AF1, AH4, AK2 AK13, AL7, AL9, AL10, AL16, AM4, AM14,AN3 AJ18, AJ25, AK28, AL20, AL24, AL29, AM26, AN23 No Connect XQVR1000 G2, G33, J32, K1, L2, M33, P1, P33, R32, T1, V33, W2, Y1, Y33, AB1, AC32, AD33, AE2, AG1, AG32, AH2, AJ33, AL32, AM3, AM7, AM11, AM19, AM25, AM28, AM33, AN1, AN2, AN5, AN10, AN14, AN16, AN20, AN22, AN27, AN33 C31, AC2, AK4, AL3 Table 2: Virtex Ceramic Column Grid (CG560) Pinout (Continued) Pin Name VCCO, Bank 3 VCCO, Bank 4 Device XQVR1000 CG560 V1, AA2, AD1, AK1, AL2 AM2, AM15, AN4, AN8, AN12 VCCO, Bank 5 AL31, AM21, AN18, AN24, AN30 VCCO, Bank 6 W32, AB33, AF33, AK33, AM32 VCCO, Bank 7 VREF, Bank 0 Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 1 Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 2 Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 3 Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 4 Within each bank, if input reference voltage is not required, all VREF pins are general I/O. VREF, Bank 5 Within each bank, if input reference voltage is not required, all VREF pins are general I/O. C32, D33, K33, N32, T33 A19, D20, D26, D29, E21, E23, E24, E27, DS028 (v1.2) November 5, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 5 QPro Virtex 2.5V Radiation Hardened FPGAs Table 3: CQFP Package (CB228) Function GND TMS IO IO IO_VREF_7 IO IO GND IO IO IO IO_VREF_7 IO GND VCCINT IO IO VCCO IO IO IO_VREF_7 IO IO IO IO IO_IRDY GND Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Bank # 7 Table 3: CQFP Package (CB228) (Continued) Function VCCO IO_TRDY VCCINT IO IO IO IO_VREF_6 IO IO VCCO IO IO IO VCCINT GND IO IO_VREF_6 IO IO IO_VREF_6 GND IO IO IO_VREF_6 IO IO IO M1 GND M0 Pin # 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 Bank # 6 R 6 www.xilinx.com 1-800-255-7778 DS028 (v1.2) November 5, 2001 Preliminary Product Specification R QPro Virtex 2.5V Radiation Hardened FPGAs Table 3: CQFP Package (CB228) (Continued) Bank # 5 Function VCCINT GCK1 VCCO GND GCKO IO IO IO IO IO_VREF_4 IO IO VCCO IO IO IO VCCINT GND IO IO_VREF_4 IO IO IO_VREF_4 GND IO IO IO_VREF_4 IO IO IO GND DONE VCCO Pin # 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 Bank # 4 Table 3: CQFP Package (CB228) (Continued) Function VCCO M2 IO IO IO IO_VREF_5 IO IO GND IO_VREF_5 IO IO IO_VREF5 IO GND VCCINT IO IO VCCO IO IO IO_VREF_5 IO IO IO Pin # 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 DS028 (v1.2) November 5, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 7 QPro Virtex 2.5V Radiation Hardened FPGAs Table 3: CQFP Package (CB228) (Continued) Function PROGRAM IO_INIT IO_D7 IO IO_VREF_3 IO IO GND IO_VREF_3 IO IO IO_VREF_3 IO_D6 GND VCCINT IO_D5 IO VCCO IO IO IO_VREF_3 IO_D4 IO IO VCCINT IO_TRDY VCCO Pin # 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 Bank # 3 Table 3: CQFP Package (CB228) (Continued) Function GND IO_IRDY IO IO IO IO_D3 IO_VREF_2 IO IO VCCO IO IO IO_D2 VCCINT GND IO_D1 IO_VREF_2 IO IO IO_VREF_2 GND IO IO IO_VREF_2 IO IO_DIN_D0 IO_DOUT_BUSY CCLK VCCO Pin # 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 Bank # 2 R 8 www.xilinx.com 1-800-255-7778 DS028 (v1.2) November 5, 2001 Preliminary Product Specification R QPro Virtex 2.5V Radiation Hardened FPGAs Table 3: CQFP Package (CB228) (Continued) Bank # 1 Function GCK3 VCCINT IO IO IO IO_VREF_0 IO IO VCCO IO IO IO VCCINT GND IO IO_VREF_0 IO IO IO_VREF_0 GND IO IO IO_VREF_0 IO IO TCK VCCO Pin # 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 Bank # 0 Table 3: CQFP Package (CB228) (Continued) Function TDO GND TDI IO_CS IO_WRITE IO IO_VREF_1 IO GND IO_VREF_1 IO IO IO_VREF_1 IO GND VCCINT IO IO IO VCCO IO IO IO_VREF_1 IO IO IO IO GCK2 GND VCCO Pin # 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 DS028 (v1.2) November 5, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 9 QPro Virtex 2.5V Radiation Hardened FPGAs Table 3: CQFP Package (CB228) (Continued) Function GND Pin # 1, 8, 14, 27, 42, 48, 56, 66, 72, 86, 100, 106, 113, 123, 129, 143, 157, 163, 173, 180, 186, 200, 215, 221 15, 30, 41, 73, 83, 99, 130, 140, 156, 187, 203, 214 18, 28, 37, 58, 76, 85, 95, 115, 133, 142, 152, 171, 191, 201, 210, 228 Bank # Table 4: Pinout Diagram Symbols (Continued) Symbol v O R r G O, 1, 2, 3 , , , , , , , , , B D DOUT/BUSY DONE PROGRAM INIT CCLK WRITE CS Boundary-scan test access port Temperature diode, anode Temperature diode, cathode No connect Pin Function Device-dependent VCCINT, n/c on smaller devices VCCO VREF Device-dependent VREF, remains I/O on smaller devices Ground Global Clocks M0, M1, M2 D0/DIN, D1, D2, D3, D4, D5, D6, D7 R VCCINT VCCO Pinout Diagrams The following diagrams illustrate the locations of special-purpose pins on Virtex FPGAs. Table 4 lists the symbols used in these diagrams. The diagrams also show I/O-bank boundaries. Table 4: Pinout Diagram Symbols Symbol S d V General I/O Device-dependent general I/O, n/c on smaller devices VCCINT Pin Function P I K W S T + - n 10 www.xilinx.com 1-800-255-7778 DS028 (v1.2) November 5, 2001 Preliminary Product Specification R QPro Virtex 2.5V Radiation Hardened FPGAs CG560 Pin Function Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN G G O G O V G O V G R G O G G O r G O P G S O G V G G O G V O v n V G G R O O G RGO r GG OK BTWR r R OT r V Bank 1 R R r Bank 2 R v r R V R R r Bank 3 R R V Bank 4 r I D n V V n R r R GRGG r OGOG G v V O r G V G R O R 3 2 G V R O G R V r O v G G V Rr Bank 0 O R G R V Bank 7 CG560 (Top View) Bank 6 Bank 5 O v r V R G O R G 1 V O R O G V R G O v G r R O R G V r V G + r G G r T v R R - R O V V r r O G n r R R R R R V R r V O G O O G r G V O G O R v G V G R G O G T O G O r G V G O G G O G O G O G G A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN DS028 (v1.2) November 5, 2001 Preliminary Product Specification 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 www.xilinx.com 1-800-255-7778 11 QPro Virtex 2.5V Radiation Hardened FPGAs R Package Drawing CG560 Ceramic Column Grid DS028_01_011900 12 www.xilinx.com 1-800-255-7778 DS028 (v1.2) November 5, 2001 Preliminary Product Specification R QPro Virtex 2.5V Radiation Hardened FPGAs Device/Package Combinations and Maximum I/O Maximum User I/O (excluding dedicated clock pins) Package CB228 CG560 XQVR300 162 XQVR600 162 XQVR1000 404 Ordering Information Example: Device Type Speed Grade(1) XQVR1000 -4 CG 560 V Manufacturing Grade Number of Pins Package Type Device Ordering Options Device Type XQVR300 XQVR600 XQVR1000 Notes: 1. -4 only supported speed grade. 2. Class Q must be ordered with SMD number. CB228 CG560 Package 228-pin Ceramic Quad Flat Package 560-column Ceramic Column Grid Package Grade M V Q Military Ceramic QPro Plus MIL-PRF-38535 (2) TC = -55C to +125C TC = -55C to +125C TC = -55C to +125C Device Ordering Combinations M Grade XQVR300-4CB228M XQVR600-4CB228M XQVR1000-4CG560M V Grade XQVR300-4CB228V XQVR600-4CB228V XQVR1000-4CG560V DS028 (v1.2) November 5, 2001 Preliminary Product Specification www.xilinx.com 1-800-255-7778 13 QPro Virtex 2.5V Radiation Hardened FPGAs R SMD (Class Q) Odering Options 5962 R 9957201 Q Y C Generic Standard Microcircuit Drawing (SMD) Lead Finish Package Type Radiation Hardened Device Type QML Certified MIL-PRF-38535 Valid SMD Combinations SMD Number 5962R9957201QYC 5962R9957201QZC 5962R9957301QYC 5962R9957301QZC 5962R9957401QXC Device XQVR300-4CB228Q XQVR300-4CB228Q XQVR600-4CB228Q XQVR600-4CB228Q XQVR1000-4CG560Q Pkg Markings Lid Base Lid Base - Lead Finish Gold Plate Gold Plate Gold Plate Gold Plate Solder Column Revision History The following table shows the revision history for this document. Date 04/25/00 02/13/01 11/05/01 Version 1.0 1.1 1.2 Initial Xilinx release. Updated TemperatureSpecifications. Updated Temp specifications for V600, Added Class V option and SMD. Updated format. Revision 14 www.xilinx.com 1-800-255-7778 DS028 (v1.2) November 5, 2001 Preliminary Product Specification |
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